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-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/20/2007
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.all;

ENTITY simple_comparator_16 IS
	PORT (	in0,in1			: IN  STD_LOGIC_VECTOR (15 DOWNTO 0);
      		q	 			: OUT STD_LOGIC
			);
END simple_comparator_16;

ARCHITECTURE behav OF simple_comparator_16 IS
BEGIN
	PROCESS (in0, in1)
	BEGIN
	IF (in0 = in1) THEN
		q <= '0';
	ELSE
		q <= '1';
	END IF;
	END PROCESS;
END behav;